VHDL语言设计分频器
输入信号10HZ的话 你要分频咯 这个频率无所谓的 主要看你分频的精度毕业设计这个层次的东西要求不会很高的 那就选25MHz的吧 最好用有源晶振无源也问题不大 呵呵绝戚我给你个万能分频代码吧 你的分数也太低了吧 0分VHDL的野宏大任颂竖意整数且占空比为50%分频代码说明如下：1.其中top file 为 division，其中的clk_com是比较的频率，用它来和分频后波形进行比较，便于观察，2.any_enve为任意偶数分频文件3.any_odd为任意奇数分频文件4.是一个用于2进制与8进制的译码器，我用它来显示在数码管上当前到底是多少分频5.以下代码在开发板上实验过，请大家放心使用，欢迎转载，但请注明出处，另外说明由于用的是quartus7.1编辑的，中间无法加中文注释，请大家慢慢读了；以下是代码：------the top file of the design divisionlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity division is port (input : in std_logic_vector(7 downto 0); clk : in std_logic; clk_out : out std_logic; clk_com : out std_logic; led1: out std_logic_vector(6 downto 0); led2: out std_logic_vector(6 downto 0); led3: out std_logic_vector(6 downto 0));end entity division;--------------------------------------------------architecture freq of division is component decoder is----decoder port(bin : in std_logic_vector(2 downto 0); de : out std_logic_vector(6 downto 0)); end component; component any_even is----any_even division generic (data_width : integer := 8 ); port(input1 : in std_logic_vector(data_width-1 downto 0); clk_in : in std_logic; clk_out : out std_logic); end component any_even; component any_odd is-----any_even division generic (data_width : integer := 8);port(input2 : in std_logic_vector(data_width - 1 downto 0); clk_in : in std_logic; clk_out : out std_logic); end component any_odd; signal temp1,temp2 : std_logic; beginu1: decoder port map(bin=>input(2)&input(1)&input(0),de=>led1);u2: decoder port map(bin=>input(5)&input(4)&input(3),de=>led2);u3: decoder port map(bin=>'0'&input(7)&input(6),de=>led3);u4: any_even port map(input,clk,temp1);U5: any_odd port map(input,clk,temp2);process(clk,input) begin if input(0)= '0' then clk_out <= temp1; else clk_out <= temp2; end if; end process;clk_com <= clk;end architecture freq;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity any_even is generic (data_width : integer := 8 ); port(input1 : in std_logic_vector(data_width-1 downto 0); clk_in : in std_logic; clk_out : out std_logic);end entity any_even; architecture div1 of any_even is signal clk_outQ : std_logic ; signal coutQ : std_logic_vector (data_width - 1 downto 0); begin------------------------------------------------- process(clk_in) begin if clk_in'event and clk_in = '1' then if coutQ < (conv_integer(input1) - 1) then coutQ <= coutQ + 1; else coutQ <= (others => '0'); end if; end if; end process;--------------------------------------------------- process(coutQ) begin if coutQ < (conv_integer(input1))/2 then clk_outQ <= '0'; else clk_outQ <= '1'; end if; end process;clk_out <= clk_outQ;end architecture div1; library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity any_odd isgeneric (data_width : integer := 8);port(input2 : in std_logic_vector(data_width - 1 downto 0); clk_in : in std_logic; clk_out : out std_logic);end entity any_odd;architecture div2 of any_odd issignal cout1,cout2 : std_logic_vector(data_width - 1 downto 0);signal clk1,clk2 : std_logic;beginprocess(clk_in)------rising edge begin if clk_in'event and clk_in='1' then if cout1 < (conv_integer(input2)-1) then cout1 <= cout1 + 1; else cout1 <= (others => '0'); end if; if cout1 < (conv_integer(input2)-1)/2 then clk1 <= '1'; else clk1 <= '0'; end if; end if;end process;---------------------------process(clk_in)------falling edge begin if clk_in'event and clk_in='0' then if cout2 < (conv_integer(input2)-1) then cout2 <= cout2 + 1; else cout2 <= (others => '0'); end if; if cout2 < (conv_integer(input2)-1)/2 then clk2 <= '1'; else clk2 <= '0'; end if; end if;end process;clk_out <= clk1 or clk2;end architecture div2;library ieee;use ieee.std_logic_1164.all;entity decoder is port(bin : in std_logic_vector(2 downto 0); de : out std_logic_vector(6 downto 0));end entity;----------------------------------------------------architecture deco of decoder is begin process(bin) begin case bin is when "000" => de <= "0111111";---0 when "001" => de <= "0000110";---1 when "010" => de <= "1011011";---2 when "011" => de <= "1001111";---3 when "100" => de <= "1100110";---4 when "101" => de <= "1101101";---5 when "110" => de <= "1111101";---6 when others => de <= "0000111";---7 end case; end process;end architecture;
标签：分频器,VHDL,语言
